Parasitic-Aware Hierarchical Symbolic Performance Modeling for Layout-Inclusive Synthesis of Large Analog Circuits

The primary focus of this work is on the generation of layout-aware symbolic performance models (SPMs), for parasitic-inclusive large analog circuits, by using exact hierarchical symbolic analysis. Two problems arise while generating these SPMs. The first problem is the symbolic analysis of large networks. We propose a new hierarchical symbolic analysis technique, that takes the modular approach of layout-generation and uses it for large circuits. The core of this algorithm is a novel idea where transfer functions are synthesized for a general interconnection template of two subcircuits. The second problem deals with the generation and partitioning of circuit topologies, that include all parasitics generated in a synthesis run. We propose efficient techniques for parasitic-inclusive topology generation and partitioning. In this paper we also use the SPMs, in layout-inclusive synthesis of a large analog circuit, to overcome important deficiencies in traditional analog synthesis. The accuracy and effectiveness of these SPMs has also been demonstrated.